Synopsys has announced that Innovium, Inc., a leading provider of networking solutions for datacentres, has adopted the Synopsys IC Validator tool for physical signoff.
Innovium deployed IC Validator on its flagship 12.8 terabit-per-second (Tbps) throughput TERALYNX switch.
To meet its aggressive time-to-market schedule, Innovium used IC Validator across more than 250 CPU cores to take advantage of IC Validator’s performance scaling.
IC Validator completed full-chip design rule checking (DRC) and layout-versus-schematic (LVS) signoff on TSMC’s 16-nanometer (nm) FinFET process within one day.
“Physical verification is on the critical path to our tapeout. Early physical verification closure is essential to ensure that design schedules are met,” said Keith Ring, Vice President of Technology at Innovium.
“IC Validator performance enabled us to complete full-chip DRC and LVS signoff within a day for our flagship network switch design.”
IC Validator, a key component of Synopsys’ Fusion Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (PERC), dummy metal fill and design-for-manufacturabilty (DFM) enhancement capabilities.
IC Validator is architected for high performance and scalability that maximises utilisation of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.
“Designers are challenged to close physical verification within schedule because of the increasing manufacturing complexity at advanced technology nodes,” said Christen Decoin, Senior Director of Business Development, Design Group at Synopsys. “Through high performance, scalability and readily available optimised runsets from all major foundries, IC Validator is providing designers with the fastest path to production silicon.”
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